The electronic display industry, in its continual quest for increasing efficiency, is constantly scaling up the areal, or sheet, size of the substrates (typically glass) carrying the pixel matrices of the displays. However, the ever-increasing substrate sizes create significant manufacturing and engineering challenges relative to their use, handling and transportation. Furthermore, the upfront capital investment in infrastructure needed to process these large sheets of glass for each subsequent generation of fabrication facility has ballooned to upwards of $2 Billion. It is interesting to note that even though the underlying substrate sizes have increased, the photolithography used in fabricating electronic displays is still performed using step and scan exposure systems, in which the exposure size is typically much smaller than the substrate size. Similarly, semiconductors in general are manufactured using multiple photolithographic steps on ever larger wafers (substrates).
Trends in the display industry, and electronics industry generally, suggest that further display and electronic products will be made on flexible/conformal substrates, and optimally although not necessarily in a roll-to-roll, or reel-to-reel fashion. This transition is seen as inevitable to service the ever-present need and desire to reduce the size, weight and cost of the products without sacrificing performance. A wide gamut of products from displays, electronics and sensors, to name a few, would benefit from processes that result in the mass production of ruggedized, lightweight, portable, small form factor, less power hungry and lower cost electronic components. In addition, new and novel markets and opportunities could be addressed and opened up if these components could be made flexible and/or conformal.
In order to counter the ever-growing substrate size dilemma and to service future flexible needs, attempts have been made, and are ongoing, to develop manufacturing processes that would allow for roll-to-roll, or reel-to-reel (also called “web coaters”), technologies to be implemented such that flexible substrates, such as polymers/plastic foils and metal foils, may be substituted for rigid glass substrates. However, attempts made have had limited success, primarily due to the complexity of manufacturing the electronic devices, such as thin-film transistors (TFTs), of the displays. Typical manufacturing processes for such devices include multiple coatings, or layers, deposited at high temperature, interspaced with multiple photolithography patterning steps.
It is commonly known that polymers/plastics, if used as substrate material for electronic devices, severely limit the maximum temperature that may be used during the manufacturing of the end product. In addition, in order to inhibit undue out-gassing and contamination of equipment and devices during coating depositions, plastic substrates need to undergo a complex and time consuming pre-bake thermal cycling step. This pre-bake step also serves to expel moisture from the native polymer substrate, thereby stabilizing its coefficient of thermal expansion, which assists in the photolithography patterning and alignment steps.
Metal foils, on the other hand, are more resilient than polymers/plastics and tend to be immune from the temperature limit imposed by polymers/plastics. However, to date, TFTs made on metal foils have exhibited low electronic performance due to contamination effects and other unknowns attributed to high surface roughness of starting metal substrates. They are also typically opaque which limits their usefulness for displays.
Furthermore, the use of flexible substrates has placed heavy demands on engineering new ways and equipment to address: dimensional stability of substrates during lithography; mechanics for handling substrate curvature; registration accuracy; and consistency of placement of TFTs and electrodes. In this connection, flexible polymer/plastic substrates have had issues with moisture absorption, resistance to chemicals and solvents.
One of the more significant of the technical challenges to using flexible substrates that has slowed or stymied attempts at roll-to-roll manufacturing of electronic devices on either polymers/plastics or metal foils is the issue with photolithography registration and photolithography alignment due to the number of coatings and photo masking steps involved in manufacturing traditional TFTs.
FIGS. 1A and 1B illustrate, respectively, a portion of an array 10 of conventional pixel cells, such as may be found in a number of active matrix backplane type displays, and a cross-section through a portion of one of the pixel cells. In this example each pixel cell 14 generally comprises a TFT 18, a storage capacitor 22 and a pixel electrode 24 made of indium tin oxide (ITO). Referring particularly to FIG. 1B, the various layers that make up each cell include a glass substrate layer 28 (e.g., a 0.7 mm thick piece of Corning 1737 glass), a gate electrode layer 32 (made of, e.g., chromium (Cr)), a gate insulator layer 36 (e.g., a silicon nitride (SiNx) layer), a pixel electrode layer 40 (made of, e.g., ITO), a channel layer 44 (e.g., an amorphous silicon (a-Si) layer), an ohmic contact layer 48 (e.g., an n+ a-Si layer), a source/drain metal electrode layer 52 (made of, e.g., Cr) and a passivation layer 56 (e.g., a SiN layer).
Following is a typical conventional set of steps, or recipe, that a manufacturer may use to form pixel cells 14 of FIGS. 1A-B:
Step #1:prepare staging area;Step #2:clean glass substrate 28;Step #3:sputter deposit gate metal layer 32;Step #4:clean, coat and cure photoresist (not shown);Step #5:align mask 1 (not shown) and expose;Step #6:develop resist, etch gate metal, strip photoresistand dry with air knives;Step #7:deposit silicon nitride layer 36, amorphous silicon (orpolysilicon) layer 44 and n+ dopant layer 48;Step #8:clean, coat and cure photoresist (not shown);Step #9:align mask 2 (not shown) and expose;Step #10:develop resist, rinse and dry with air knives;Step #11:dry etch a-Si pattern into layers 44 and 48 andstrip photoresist;Step #12:ultrasonic clean;Step #13:sputter deposit ITO layer 40;Step #14:clean, coat and cure photoresist (not shown);Step #15:align mask 3 (not shown) and expose;Step #16:develop, etch ITO layer 40, strip photoresist anddry with air knives;Step #17:sputter deposit S/D and interconnect metal layer 52;Step #18:clean, coat and cure photoresist (not shown);Step #19:align mask 4 (not shown) and expose;Step #20:develop, etch S/D and interconnect metal layer 48,strip photoresist and dry with air knives;Step #21:dry etch n+ doped layer 48;Step #22:deposit passivation layer 56 using plasma-enhancedchemical vapor deposition;Step #23:clean, coat and cure photoresist (not shown);Step #24:align mask 5 (not shown) and expose;Step #25:develop and rinse photoresist and dry with air knives;Step #26:dry etch passivation layer and strip photoresist;Step #27:ultrasonic clean;Step #28:test and review; andStep #29:laser repair shorts.It is noted that this recipe is for a traditional rigid platform. Converting this to a roll-to-roll process may also require intermediary steps of unwinding and rewinding the substrate roll between steps if the process is not continuous, and some degree of winding and unwinding is unavoidable in transporting the working substrate between stations in a continuous process. Note in the foregoing recipe the number of masks required, each requiring that a mask must be aligned in order for the corresponding subsequently patterned layer to be in proper registration with the other layers so as to create properly functioning devices. These alignment steps are a hindrance to achieving high device yield and efficient processing, especially in a roll-to-roll process wherein these alignment steps must be performed in conjunction with unwinding and rewinding, which makes the aligning all the more difficult.
Various efforts to date have demonstrated low pixel density TFTs having marginal performance on metal/polyimide substrates. However, what is really needed by the industry as a whole is a methodology that uses a low mask count TFT design and that has roll-to-roll continuous processing capability and that utilizes techniques and equipment that circumvent issues such as photolithography registration and alignment. The present invention includes such a methodology that essentially renders irrelevant dimensional stability of the substrate due to temperature and allows for the realization of high-resolution displays and the fabrication of other electronic products.